The present invention relates to system switching circuits and more particularly to a system switching circuit for a system in which a host apparatus having an active (ACT) system and a hot-standby (SBY) system and a slave apparatus are provided, wherein signals from the two systems of the host apparatus merge into each other and a signal from the ACT system of the host apparatus is selected by the slave apparatus.
For example, JP-A-5-2438 proposes, as a system switching circuit for switching a serving system and a preliminary system, a circuit configuration capable of maintaining continuity of clocks upon clock switching. In the proposed circuit, a phase control signal for the clock of the serving system is fixed and a phase control signal for the clock of the preliminary system is changed in accordance with a clock phase difference signal delivered out of a phase comparator so that the phase of the clock of the preliminary system may always be matched to the phase of the clock of the serving system.
More particularly, a conventional circuit of this type as shown in FIG. 4 has a phase comparator circuit 105, which is an analog circuit, adapted to compare the phase of the clock of the serving system with the phase of the clock of the preliminary system. In the phase comparator circuit, a flip-flop is set and reset by rise edges of input clocks of "0" system and "1" system to produce a pulse signal having a pulse width corresponding to a phase difference between the clocks of the serving and preliminary systems, the pulse signal is integrated with time by means of an integrating circuit so as to be converted into a voltage value proportional to the phase difference, and the voltage value is converted into a clock phase difference signal 106 of parallel data by means of an analog/digital (A/D) converter. The clock phase difference signal 106 is delivered to a phase controller 107. The phase controller 107 acts on programmable delay lines (PDL's) 110 and 111 for phase adjustment which are provided for the serving and preliminary systems in such a way that the output data of the controller 107 is fixed for the PDL 110 of the serving system clock but the output data of the controller 107 is changed for the PDL 111 of the preliminary system clock in accordance with the clock phase difference to match the clock of the preliminary system to the phase of the clock of the serving system. A selector 115 receives the clocks 112 and 113 of "0" system and "1" system to select one of received "0" system ACT signal 103 and "1" system ACT signal 104 and delivers the selected signal. Since the clocks 112 and 113 of the "0" system and "1" system after the phase adjustment are always kept to be in phase, continuity of clocks can be maintained when switching is effected between the clocks of the serving and preliminary systems.
However, the above prior art describes its main purpose as being directed to only phase synchronization of clocks and gives no description of a system switching circuit for a system in which serial data and a pulse indicative of the head of the data are transmitted simultaneously.
Further, in the prior art, the comparison of clock phases is of the analog type using the integrating circuit which requires troublesome adjustments and cannot meet digital integration.